The present invention relates to the field of electronic circuits, and, more particularly, to a process for manufacturing non-volatile memory cells integrated on a semiconductor substrate, such as flash EEPROM cells.
Specifically, the invention relates to a process for manufacturing electronic non-volatile memory devices which are integrated on a semiconductor substrate and constructed with a matrix of memory cells having floating gate regions formed for respective active areas.
The invention particularly, but not exclusively, relates to an improved method of planarizing matrices of non-volatile memory cells, such as flash EEPROM memory cells. The description which follows will make reference to this application field for convenience of explanation only.
As is well known in the art, semiconductor integrated electronic flash EEPROM memory devices include a plurality of non-volatile memory cells which are organized in matrix form. That is, the cells are organized into rows (or word lines) and columns (or bit lines). Each non-volatile memory cell includes a MOS transistor provided with a floating gate above its channel region, i.e., an electrode having a high direct impedance to all the other terminals of the same cell and of the circuit where the cell is connected.
The cell also includes a second electrode, the control gate, which is driven by appropriate control voltages. Of course, the transistor also includes drain and source electrodes. A known process flow for manufacturing flash EEPROM memory cells 1 integrated in a semiconductor substrate 2 is illustrated in FIGS. 1A-1E. In these figures there are shown vertical cross-sections taken along a parallel direction to the word lines but shifted therefrom to highlight the standard process steps in those areas.
This prior art process provides a plurality of active areas formed in the substrate. The memory cells to be formed later will be separated from one another by portions of a field oxide layer FOX. On the substrate 2, a first dielectric layer 3, known as the tunnel oxide, and a layer 4 of polycrystalline silicon, are then formed. Thereafter, the layer 4 is patterned to provide a plurality of polycrystalline silicon strips 5, known as floating gates, which are parallel to one another. Such strips 5 are separated and isolated from the substrate 2 by the oxide layer 3, as shown in FIG. 1B.
Following deposition of an interpoly dielectric layer 6, the standard process flow includes defining the word lines 7 by forming a layer 8 of polycrystalline silicon (known as Poly2) and a layer 9 of a metallic silicide MSix, where the metal may be tungsten or cobalt, for example.
This metallic silicide layer 9 is cascaded onto, or formed in situ, by a silicidation process on the previously defined Poly2 layer. The word lines 7 are then defined by a photolithographic process using a resist mask such that such word lines 7 will lie perpendicular to the floating gate strips 5. The word lines 7 and floating gate strips 5 typically are defined using a xe2x80x9cself-aligned cellxe2x80x9d technique including a series of plasma etching operations which may be carried out sequentially or in several operations optionally separated by suitable cleaning steps between an etch step and another step.
In the latter case, the etching of the word lines 7 including silicide/Poly2 reaches the interpoly oxide layer 6. While having many advantageous aspects, this prior art process has drawbacks. This memory cell patterning is actually subject to faults due the cell morphology. In fact, the spacing of the floating gate strips 5 causes corrugations to appear in the Poly2 layer 8 deposited over the floating gate strips 5, with hollows of increasing depth as the dimensions of the device are scaled, as shown in FIG. 1C.
This results in the development of possible cracks 10 in the metallic silicide layer 9 of the word lines. Such cracks 10 are more likely to appear after the cell is sealed by thermal oxidation, upon completion of its patterning, and especially in devices having a layer of WSix deposited over the Poly2 layer. In the latter devices, the deposition of a second layer 9 intensifies this creasing effect and, with it, the strain on the deposited silicide film.
Faults of this kind give rise to two major disadvantages. First, a high resistance of the word lines 7 and associated negative effects on the electrical performances of the device may result. Also, where an organic anti-reflection layer is used in patterning the matrix, an increased rate of rejects or increased redundancy consumption due to shorts occurring between rows and/or cells may occur. The anti-reflection layer would penetrate cracks 10, and if its etching is dedicated and non-selective to the silicide layer 9, removal of the layers of Poly2 8 and silicide 9 would cause the formation of residues 11, as shown in FIG. 1E.
Another important aspect of patterning matrices which include flash memory cells is the etching used for the removal of the interpoly dielectric layer 6 to define the source and drain lines in the substrate, as shown in FIG. 1F. This operation causes the loss of a certain thickness of the exposed insulating dielectric at the end of the MSix/Poly2 etching. A reduced thickness of the field oxide may cause the possible failure of the channel insulation upon implantation (i.e., the formation of shifts).
The underlying technical problem of this invention is to provide a process for manufacturing non-volatile memory cells with structural features able to reduce cracking at the word lines and preserve the insulation during the cell patterning, such that the drawbacks present in prior art devices may be overcome.
An object of the invention is to provide patterning of the floating gate regions with sidewalls slanted with respect to the surface of the substrate along a parallel direction to the word lines.
These and other objects, features, and advantages in accordance with the present invention are provided by a method for manufacturing electronic non-volatile memory devices on a semiconductor substrate including a matrix of memory cells having floating gate regions formed on respective active areas and an oxide layer separating the active areas. The method may include forming sidewalls of the floating gate regions that are slanted with respect to a surface of the semiconductor substrate, forming a trench in the oxide layer following the formation of the floating gate regions, and forming a plug of polycrystalline silicon in the trench. The slanted sidewalls of the floating gate regions provide a lead-in for the formation of upper layers.
More particularly, the floating gate regions may be formed by end-point etching. Furthermore, the walls of the floating gate regions may be slanted at an inclination angle of less than 85xc2x0 with respect to the surface of the semiconductor substrate. The trench may be formed by over-etching through the oxide layer. Also, the plug may fill only a portion of the trench.
A memory device according to the invention includes a semiconductor substrate, an oxide layer defining spaced apart active areas in the semiconductor substrate, a floating gate region on each respective active area, and at least one plug in the oxide layer. The sidewalls may be slanted with respect to a surface of the semiconductor substrate.